Features of the transition process of establishing the duration of output pulses in a braked relaxation oscillator with a shaping RS flip-flopEROFEEV, YU. N.Journal of communications technology & electronics. 1997, Vol 42, Num 5, pp 574-580, issn 1064-2269Article

Design of high performance double edge-triggered flip-flopsMISHRA, S. M; ROFAIL, S. S; YEO, K. S et al.IEE proceedings. Circuits, devices and systems. 2000, Vol 147, Num 5, pp 283-290, issn 1350-2409Article

Analysis of power dissipation in double edge-triggered flip-flopsSTROLLO, Antonio G. M; NAPOLI, Ettore; CIMINO, Carlo et al.IEEE transactions on very large scale integration (VLSI) systems. 2000, Vol 8, Num 5, pp 624-629, issn 1063-8210Conference Paper

Noise metrics in flip-flop designsELGAMEL, Mohammed A; FAISAL, Md Ibrahim; BAYOUMI, Magdy A et al.IEICE transactions on information and systems. 2005, Vol 88, Num 7, pp 1501-1505, issn 0916-8532, 5 p.Article

High performance double edge-triggered flip-flop using a merged feedback techniqueMISHRA, S. M; ROFAIL, S. S; YEO, K.-S et al.IEE proceedings. Circuits, devices and systems. 2000, Vol 147, Num 6, pp 363-368, issn 1350-2409Article

Low voltage, double-edge-triggered flip flopVARMA, Pradeep; CHAKRABORTY, Ashutosh.Lecture notes in computer science. 2003, pp 11-20, issn 0302-9743, isbn 3-540-20074-6, 10 p.Conference Paper

A novel 2.4 GHz CMOS dual-modulus prescaler using new implementation of phase-switching techniqueBAOYONG CHI; BINGXUE SHI.International journal of electronics. 2002, Vol 89, Num 6, pp 505-515, issn 0020-7217, 11 p.Article

Improving path delay testability of sequential circuitsCHAKRABORTY, Tapan J; AGRAWAL, Vishwani D; BUSHNELL, Michael L et al.IEEE transactions on very large scale integration (VLSI) systems. 2000, Vol 8, Num 6, pp 736-741, issn 1063-8210Article

Self-blocking flip-flop designLI, X; JIA, S; LIANG, X et al.Electronics letters. 2012, Vol 48, Num 2, pp 82-83, issn 0013-5194, 2 p.Article

Microthyristor-based sequential circuits and systemsHAFEZ, I. M; ZEKRY, A.International journal of electronics. 2004, Vol 91, Num 2, pp 119-135, issn 0020-7217, 17 p.Article

All-optical switching based on a three-order scattering of light by coherent acoustic phonons in single crystalsSHCHERBAKOV, Alexandre S; TEPICHIN RODRIGUEZ, Eduardo; AGUIRRE LOPEZ, Arturo et al.SPIE proceedings series. 2002, pp 239-247, isbn 0-8194-4555-X, 9 p.Conference Paper

A new reduced clock-swing flip-flop: NAND-type keeper flip-flop (NDKFF)TOKUMASU, Motoki; FUJII, Hiroshige; OHTA, Masako et al.Custom integrated circuits conference. 2002, pp 129-132, isbn 0-7803-7250-6, 4 p.Conference Paper

Deterministic built-in test pattern generation for high-performance circuits using twisted-ring countersCHAKRABARTY, Krishnendu; MURRAY, Brian T; IYENGAR, Vikram et al.IEEE transactions on very large scale integration (VLSI) systems. 2000, Vol 8, Num 5, pp 633-636, issn 1063-8210Conference Paper

Electrical bistability and spin valve effect in a ferromagnet/organic semiconductor/ferromagnet heterojunctionBIN LI; YOO, Jung-Woo; KAO, Chi-Yueh et al.Organic electronics (Print). 2010, Vol 11, Num 6, pp 1149-1153, issn 1566-1199, 5 p.Article

Loss and recovery of bistability of organic bistable devicesWANG, M. L; SUN, X. Y; ZHENG, X. Y et al.Organic electronics (Print). 2009, Vol 10, Num 5, pp 965-969, issn 1566-1199, 5 p.Article

Bistability and improved hole injection in organic bistable light-emitting diodes using a quantum dot embedded hole transport layerSOON OK JEON; KYOUNG SOO YOOK; JUN YEOB LEE et al.Synthetic metals. 2010, Vol 160, Num 11-12, pp 1216-1218, issn 0379-6779, 3 p.Article

Impact of Random Dopant Fluctuations on the Timing Characteristics of Flip-FlopsFAIZ-UL-HASSAN; VANDERBAUWHEDE, Wim; RODRIGUEZ-SALAZAR, Fernando et al.IEEE transactions on very large scale integration (VLSI) systems. 2012, Vol 20, Num 1, pp 157-161, issn 1063-8210, 5 p.Article

Low-Swing Differential Conditional Capturing Flip-Flop for LC Resonant Clock Distribution NetworksESMAEILI, Seyed E; AL-KAHLILI, Asim J; COWAN, Glenn E. R et al.IEEE transactions on very large scale integration (VLSI) systems. 2012, Vol 20, Num 8, pp 1547-1551, issn 1063-8210, 5 p.Article

Iterative timing analysis based on nonlinear and interdependent flipflop modellingCHEN, N; LI, B; SCHLICHTMANN, U et al.IET circuits, devices & systems (Print). 2012, Vol 6, Num 5, pp 330-337, issn 1751-858X, 8 p.Article

Low-power programmable divider with a shared counter for frequency synthesiserKIM, K.-Y; MIN, Y.-J; KIM, S.-W et al.IET circuits, devices & systems (Print). 2011, Vol 5, Num 3, pp 170-176, issn 1751-858X, 7 p.Article

Statistical Design Framework of Submicron Flip-Flop Circuits Considering Process VariationsSAYED ALIREZA SADROSSADAT; MOSTAFA, Hassan; ANIS, Mohab et al.IEEE transactions on semiconductor manufacturing. 2011, Vol 24, Num 1, pp 69-79, issn 0894-6507, 11 p.Article

Low-power pulse-triggered flip―flop design using gated pull-up control schemeLIN, J.-F.Electronics letters. 2011, Vol 47, Num 24, pp 1313-1314, issn 0013-5194, 2 p.Article

Magnetostatic bistable MEMS switch with electrothermal actuatorsWU, Y. B; DING, G. F; ZHANG, C. C et al.Electronics letters. 2010, Vol 46, Num 15, pp 1074-1075, issn 0013-5194, 2 p.Article

43 Gb/s decision circuits in InP DHBT technologyKRISHNAMURTHY, Karthikeyan; CHOW, Jimmy; MENSA, Dino et al.IEEE microwave and wireless components letters. 2004, Vol 14, Num 1, pp 28-30, issn 1531-1309, 3 p.Article

Comparative study on low-power high-performance standard-cell flip-flopsTAHMASBI OSKUII, S; ALVANDPOUR, A.SPIE proceedings series. 2004, pp 390-398, isbn 0-8194-5167-3, 9 p.Conference Paper